1. Field of the Invention
The invention relates to a programmable logic unit for executing dyadic or monadic operations and bit-wise operations on data, presented to inputs of the unit, under the control of instructions presented to control inputs. The invention also relates to a signal processor comprising a plurality of parallel-operating programmable logic unit sections, one for each output bit position.
2. Description of the Prior Art
A publication of the "6.sup.th Symposium on Computer Arithmetic", June 20-22, 1983, Aarhus, Denmark, pages 10-16, discloses an arithmetic and logic unit which is capable of executing not only dyadic and monadic operations but also adding operations and is also capable of processing and generating carry signals. In many digital signal processing applications, however, adding operations and carry signals are not required, so that in those cases the processing of digital signals by the arithmetic and logic unit is slower than actually necessary. From said publications it is also known to use several arithmetic and logic unit sections in parallel for the execution of multi-bit operations. Such a parallel-operating unit (ALU) is described, for example in U.S. Pat. No. 4,498,135 where the ALU is connected between on the one side a shifter connected to one input, a multiplier connected to the other input and an accumulator connected to the output. Such a configuration offers a versatile tool for executing logic and arithmetic operations, but usually executes operations very inefficiently in time, because it is necessary to traverse an excessive number of stages which need not execute an operation at that instant.